AMCC Proprietary 208
Revision 1.02 - September 10, 2007
PPC405 Processor
dcbz
Data Cache Block Set to Zero
Preliminary User’s Manual
dcbz
Data Cache Block Set to Zero
EA ← (RA|0) + (RB)
DCBZ(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the data block at the EA is in the data cache and the EA is marked as cacheable and non-write-through, the data
in the cache block is set to 0.
If the data block at the EA is not in the data cache and the EA is marked as cacheable and non-write-through, a
cache block is established and set to 0. Note that nothing is read from main storage, as described in the program-
ming note.
If the data block at the EA is marked as either write-through or as non cacheable, an alignment exception occurs.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•None
Invalid Instruction Forms
• Reserved fields
Programming Notes
Because dcbz can establish an address in the data cache without copying the contents of that address from main
storage, the address established may be invalid with respect to the storage subsystem. A subsequent operation
may cause the address to be copied back to main storage, for example, to make room for a new cache block; a
machine check exception could occur under these circumstances.
If dcbz is attempted to an EA which is marked as non cacheable, the software alignment exception handler should
emulate the instruction by storing zeros to the block in main storage. If a data block corresponding to the EA exists
in the cache, but the EA is non cacheable, stores (including dcbz) to that address are considered programming
errors (the cache block should previously have been flushed).
If the EA is marked as write-through, the software alignment exception handler should emulate the instruction by
storing zeros to the block in main storage. An EA that is marked as write-through required should also be marked
as cacheable; when dcbz is attempted to such an address, the alignment exception handler should maintain
coherency of cache and memory.
Exceptions
An alignment exception occurs if the EA is marked as non cacheable or as write-through.
This instruction is considered a “store” with respect to data storage exceptions. See Data Storage Interrupt on
page 120.
dcbz RA, RB
31
RA RB 1014
0 6 11 16 21 31
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