AMCC PPC405 - Page 209

AMCC Proprietary 209
Revision 1.02 - September 10, 2007
PPC405 Processor
dcbz
Data Cache Block Set to Zero
Preliminary User’s Manual
This instruction is considered a “store” with respect to data address compare (DAC) debug exceptions. See Debug
Interrupt on page 128.
Architecture Note
This instruction is part of the PowerPC Embedded Virtual Environment.