AMCC Proprietary 210
Revision 1.02 - September 10, 2007
PPC405 Processor
dccci
Data Cache Congruence Class Invalidate
Preliminary User’s Manual
dccci
Data Cache Congruence Class Invalidate
EA ← (RA|0) + (RB)
DCCCI(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
Both cache lines in the congruence class specified by EA
18:26
are invalidated, whether or not they match the EA. If
modified data existed in the cache congruence class before the operation of this instruction, that data is lost.
The operation specified by this instruction is performed whether or not the EA is marked as cacheable.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•None
Invalid Instruction Forms
• Reserved fields
Programming Note
Execution of this instruction is privileged.
This instruction is intended for use in the power-on reset routine to invalidate the entire data cache tag array before
enabling the data cache. A series of dccci instruction should be executed, one for each congruence class. Cach-
ability can then be enabled.
Exceptions
See Access Protection for Cache Control Instructions on page 104.
The execution of an dccci instruction can cause a data TLB miss exception, at the specified EA, regardless of the
non-specific intent of that EA.
This instruction does not cause data address compare (DAC) debug exceptions. See Debug Interrupt on page 128.
Architecture Note
This instruction is implementation-specific and may not be portable to other implementations.
dccci RA, RB
31
RA RB 454
0 6 11 16 21 31
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