AMCC Proprietary 231
Revision 1.02 - September 10, 2007
PPC405 Processor
lhaux
Load Halfword Algebraic with Update Indexed
Preliminary User’s Manual
lhaux
Load Halfword Algebraic with Update Indexed
EA ← (RA) + (RB)
(RA)
← EA
(RT)
← EXTS(MS(EA,2))
An effective address (EA) is formed by adding an index to the base address in register RA. The index is the
contents of register RB. The EA is placed into register RA.
The halfword at the EA is sign-extended to 32 bits and placed into register RT.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•RA
•RT
Invalid Instruction Forms
• Reserved fields
•RA=RT
•RA=0
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
lhaux RT, RA, RB
31 RT RA RB 375
0 6 11 16 21 31
To Next Page
Loading...