AMCC PPC405 - Page 305

AMCC Proprietary 305
Revision 1.02 - September 10, 2007
PPC405 Processor
sraw
Shift Right Algebraic Word
Preliminary User’s Manual
sraw
Shift Right Algebraic Word
n ← (RB)
27:31
r ← ROTL((RS), 32 – n)
if (RB)
26
= 0 then
m
← MASK(n, 31)
else
m
←
32
0
s
← (RS)
0
(RA) ← (r ∧ m) ∨ (
32
s ∧¬m)
XER[CA]
← s ∧ ((r ∧¬m) ≠ 0)
The contents of register RS are shifted right by the number of bits specified the contents of register RB
27:31
. Bits
shifted out of the least significant bit are lost. Register RS
0
is replicated to fill the vacated positions on the left. The
result is placed into register RA.
If register RS contains a negative number and any 1-bits were shifted out of the least significant bit position,
XER[CA] is set to 1; otherwise, it is set to 0.
If bit 26 of register RB contains 1, register RA and XER[CA] are set to bit 0 of register RS.
Registers Altered
•RA
• XER[CA]
• CR[CR0]
LT, GT, EQ, SO
if Rc contains 1
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
sraw RA, RS, RB Rc=0
sraw. RA, RS, RB Rc=1
31 RS RA RB 792 Rc
0 6 11 16 21 31