AMCC Proprietary 306
Revision 1.02 - September 10, 2007
PPC405 Processor
srawi
Shift Right Algebraic Word Immediate
Preliminary User’s Manual
srawi
Shift Right Algebraic Word Imme diate
n ← SH
r
← ROTL((RS), 32 – n)
m ← MASK(n, 31)
s
← (RS)
0
(RA) ← (r ∧ m) ∨ (
32
s ∧¬m)
XER[CA] ← s ∧ ((r ∧¬m)≠0)
The contents of register RS are shifted right by the number of bits specified in the SH field. Bits shifted out of the
least significant bit are lost. Bit RS
0
is replicated to fill the vacated positions on the left. The result is placed into
register RA.
If register RS contains a negative number and any 1-bits were shifted out of the least significant bit position,
XER[CA] is set to 1; otherwise, it is set to 0.
Registers Altered
•RA
• XER[CA]
• CR[CR0]
LT, GT, EQ, SO
if Rc contains 1
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
srawi RA, RS, SH Rc=0
srawi. RA, RS, SH Rc=1
31 RS RA SH 824 Rc
0 6 11 16 21 31
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