Figure 13: SCG with RJ-48 ports
g006052
EXTERNAL CLOCK INPUTS
OK
Fail Master
Online/Offline button
Each SCG consists of the following components:
•
19.44-MHz Stratum 3 clock.
•
Field-programmable gate array (FPGA) that performs multiplexing of clock sources.
These components are located on the SCG faceplate:
•
Three LEDs—OK, FAIL, and MASTER, that display the status of the SCG.
•
SCG online/offline button.
•
Two external clock inputs.
NOTE: Junos OS Release 10.4 and later supports the external clock inputs
on the SCG with RJ-48 ports. The external clock inputs are not supported
on the SONET Clock Generator (SCG) with DB-9 ports.
For information about configuring external clock synchronization for T
Series routers, see Junos OS Administration Library
•
Two LEDs for each RJ-48 external clock input that display the status of the links.
Related
Documentation
T640 Hardware Component Overview on page 13•
• T640 SONET Clock Generators (SCGs) LEDs on page 28
• Replacing a T640 SCG on page 277
• Maintaining the T640 SCGs on page 443
• T640 RJ-48 Connector Pinouts for the SCG EXTERNAL CLOCK INPUTS Ports
• T640 Component Serial Number Label Locations on page 486
T640 SONET Clock Generators (SCGs) LEDs
Three LEDs, located on the SCG faceplate, display the status of the SCG.
Table 10 on page 29 describes the functions of the SCG LEDs. Two LINK LEDs, located
Copyright © 2017, Juniper Networks, Inc.28
T640 Core Router Hardware Guide
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