Reference Information for Remote Control
R&S
®
SMW200A
1325User Manual 1175.6632.02 ─ 30
Event status enable register (ESE)
1. Execute *ESE 1
Sets the OPC mask bit (bit No. 0) of the Standard Event Status Register (ESR) to 1
2. Send the overlapped command without *OPC, *OPC? or *WAI.
Example: INIT; *OPC?
3. Poll the operation complete state periodically (with a timer) using the sequence:
*OPC; *ESR?
A return value (LSB) of 1 indicates that the overlapped command has finished.
D.1.4.2 Examples to Command Sequence and Synchronization
See the following examples to command sequences and synchronization. Some exam-
ples given illustrate possible constellations for overlapping tasks.
Example: Commands and queries in one message
The response to a query combined in a program message with commands that affect
the queried value is not predictable.
The following commands always return the specified result:
:FREQ:STAR 1GHZ;SPAN 100 :FREQ:STAR?
Result:
1000000000 (1 GHz)
Whereas the result for the following commands is not specified by SCPI:
:FREQ:STAR 1GHz;STAR?;SPAN 1000000
The result could be the value of STARt before the command was sent since the instru-
ment might defer executing the individual commands until a program message termi-
nator is received. The result could also be 1 GHz if the instrument executes commands
as they are received.
Example: Overlapping command with *OPC
The instrument implements *RST as an overlapped command. Assuming that *RST
takes longer to execute than *OPC, sending the following command sequence results
in initiating a reset and, after some time, setting the OPC bit in the ESR:
*RST; *OPC
Sending the following commands still initiates a reset:
*RST; *OPC; *CLS
However, since the operation is still pending when the instrument executes *CLS, forc-
ing it into the "Operation Complete Command Idle" State (OCIS), *OPC is effectively
skipped. The OPC bit is not set until the instrument executes another *OPC command.
Additional Basics on Remote Control
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