Protocol analysis
R&S
®
RTP
537User Manual 1337.9952.02 ─ 12
See also: Chapter 13.1.1, "Setup - general settings", on page 512
SCLK
Defines the settings for the clock line.
SCLK source ← SCLK
Sets the input channel of the clock line. Waveform 1 of channel signals, math wave-
forms, and reference waveforms can be used for decoding.
Alternatively, digital channels can be used if MSO option R&S RTP-B1 is installed. Dig-
ital and analog channels cannot be used at the same time.
For triggering on a serial bus, analog or digital channel sources are required.
Remote command:
BUS<m>:SPI:SCLK:SOURce on page 1587
Polarity ← SCLK
Two settings define the clock mode: the clock polarity and the clock phase. Together,
they determine the edges of the clock signal on which the data are driven and sam-
pled. A master/slave pair must use the same parameter pair values to communicate.
The clock polarity is "Idle low" (idle = 0) or "Idle high" (idle = 1).
The clock phase defines the slope. It selects if data is stored with the rising or falling
slope of the clock. The slope marks the begin of a new bit.
SPI bus (option R&S
RTP-K1)
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