Rohde & Schwarz RTP044 - Pcie (Option R&S RTP-K72;K73); The Pcie Protocol

Protocol analysis
R&S
®
RTP
873User Manual 1337.9952.02 ─ 12
3. Tap "Source" and select the serial bus that is set to SpaceWire (e.g. "SB1", unless
already selected).
4. Specify search criteria according to Chapter 13.21.5.1, "SpaceWire search setup",
on page 870.
5. To acquire a waveform, press [Single].
The R&S RTP performs a SpaceWire decode according to the thresholds and pro-
tocol settings of the associated serial bus source.
6. To start searching the acquired waveform for specific events, tap "Enable" in the
search setup dialog:
The R&S RTP displays the "Search Results" box that lists the detected events.
For information on how to configure the search results presentation and how to navi-
gate the search results, see also "To display search zoom windows" on page 470.
13.22 PCIe (option R&S RTP-K72/K73)
R&S RTP-K72 is a firmware option that enables the R&S RTP to analyze Peripheral
Component Interconnect Express (PCIe) signals encoded by the PCIe standard, gen-
eration 1 and 2.
With option R&S RTP-K73, you can also analyze PCIe standard, generation 3 signals.
For analysis, PCIe encoded signals can be triggered, decoded and searched.
● The PCIe protocol................................................................................................. 873
● PCIe configuration.................................................................................................876
● PCIe digital signal processing (DSP) settings.......................................................879
● PCIe trigger...........................................................................................................883
● PCIe Gen 1/2 decode results................................................................................894
● PCIe Gen 1/2 search.............................................................................................895
13.22.1 The PCIe protocol
The PCIe is a high-speed serial computer expansion bus standard.
The communication between two PCIe devices is performed through logical connec-
tions called links. Each link consists of several lanes. The lanes contain one differential
signaling pair for receiving data and the other for transmitting it.
PCIe logical layers
The PCIe has three logical layers:
●
Transaction layer: assembles and disassembles transaction layer packets (TLPs).
TLP transfer information like read and write and some event types.
PCIe (option R&S
RTP-K72/K73)