EasyManuals Logo

ST STM32F207 series User Manual

ST STM32F207 series
1381 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #1026 background imageLoading...
Page #1026 background image
USB on-the-go full-speed (OTG_FS) RM0033
1026/1381 RM0033 Rev 9
OTG_FS device IN endpoint FIFO empty interrupt mask register:
(OTG_FS_DIEPEMPMSK)
Address offset: 0x834
Reset value: 0x0000 0000
This register is used to control the IN endpoint FIFO empty interrupt generation
(TXFE_OTG_FS_DIEPINTx).
OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
Address offset: 0x900
Reset value: 0x0000 0000
This section describes the OTG_FS_DIEPCTL0 register. Nonzero control endpoints use
registers for endpoints 1–3.
313029282726252423222120191817161514131211109876543210
Reserved
DVBUSP
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DVBUSP: Device V
BUS
pulsing time
Specifies the V
BUS
pulsing time during SRP. This value equals:
V
BUS
pulsing time in PHY clocks / 1 024
313029282726252423222120191817161514131211109876543210
Reserved
INEPTXFEM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits
These bits act as mask bits for OTG_FS_DIEPINTx.
TXFE interrupt one bit per IN endpoint:
Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3
0: Masked interrupt
1: Unmasked interrupt
313029282726252423222120191817161514131211109876543210
EPENA
EPDIS
Reserved
SNAK
CNAK
TXFNUM
STALL
Reserved
EPTYP
NAKSTS
Reserved
USBAEP
Reserved
MPSIZ
r r w w rw rw rw rw rs r r r r rw rw

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ST STM32F207 series and is the answer not in the manual?

ST STM32F207 series Specifications

General IconGeneral
BrandST
ModelSTM32F207 series
CategoryMicrocontrollers
LanguageEnglish

Related product manuals