ST STM32F207 series User Manual

Memory and bus architecture RM0033
48/1381 RM0033 Rev 9
2 Memory and bus architecture
2.1 System architecture
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
• Height masters:
–Cortex
®
-M3 core I-bus, D-bus and S-bus
– DMA1 memory bus
– DMA2 memory bus
– DMA2 peripheral bus
– Ethernet DMA bus
– USB OTG HS DMA bus
• Seven slaves:
– Internal Flash memory ICode bus
– Internal Flash memory DCode bus
– Main internal SRAM1 (112 KB)
– Auxiliary internal SRAM2 (16 KB)
– AHB1peripherals including AHB to APB bridges and APB peripherals
– AHB2 peripherals
–FSMC
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 1.

ST STM32F207 series Specifications

General

Brand	ST
Model	STM32F207 series
Category	Microcontrollers
Language	English