General-purpose timers (TIM9 to TIM14) RM0033
460/1381 RM0033 Rev 9
15.4.2 TIM9/12 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
1514131211109876543210
Reserved
MMS[2:0]
Reserved
rw rw rw
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:4 MMS[2:0]: Master mode selection
These bits are used to select the information to be sent in Master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit in the TIMx_EGR register is used as the trigger output (TRGO). If
the reset is generated by the trigger input (slave mode controller configured in reset mode)
then the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as the trigger output (TRGO). It
is useful to start several timers at the same time or to control a window in which a slave timer
is enabled. The Counter Enable signal is generated by a logic OR between the CEN control
bit and the trigger input when configured in Gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR
register).
010: Update - The update event is selected as the trigger output (TRGO). For instance a
master timer can be used as a prescaler for a slave timer.
011: Compare pulse - The trigger output sends a positive pulse when the CC1IF flag is to
be set (even if it was already high), as soon as a capture or a compare match occurs.
(TRGO).
100: Compare - OC1REF signal is used as the trigger output (TRGO).
101: Compare - OC2REF signal is used as the trigger output (TRGO).
110: Reserved
111: Reserved
Note: The clock of the slave timer and ADC must be enabled prior to receiving events from
the master timer, and must not be changed on-the-fly while triggers are received from
the master timer.
Bits 3:0 Reserved, must be kept at reset value.
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