ST STM32F207 series - Figure 410. Multiplexed Read Accesses; Figure 411. Multiplexed Write Accesses

Flexible static memory controller (FSMC) RM0033
1284/1381 RM0033 Rev 9
Muxed mode - multiplexed asynchronous access to NOR Flash memory
Figure 410. Multiplexed read accesses
Figure 411. Multiplexed write accesses
The difference with mode D is the drive of the lower address byte(s) on the databus.
A[25:16]
NOE
ADDSET (DATAST + 1)
Memory transaction
NEx
AD[15:0]
HCLK cycles HCLK cycles
NWE
NADV
data driven by FSMC
ai15569
1HCLK
ADDHLD
HCLK cycles
Lower address