ST STM32F207 series - Figure 211. Block Diagram

Hash processor (HASH) RM0033
550/1381 RM0033 Rev 9
Figure 211. Block diagram
32-bit AHB2 bus
Hash / HMAC
SHA-1 / MD5
HASH_DIN
swa ppin g
16 × 32-bit
IN FIFO
HASH_CR
HASH_H0...H4
HASH_CSR0..50
context
digest
HASH_IMR
HASH_SR
Interrupt registers
Control register
Context swapping
Message digest
processor core
HASH_ST R
Start register
IN FIFO full
write into HASH_DIN
Control and status
registers
Data
register
or write DCAL bit to 1
or 1 complete block
or DCAL written to 1
IN buffer
transferred by the DMA
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