ST STM32F207 series User Manual

RM0033 Rev 9 181/1381
RM0033 DMA controller (DMA)
211
9.3.4 Arbiter
An arbiter manages the 8 DMA stream requests based on their priority for each of the two
AHB master ports (memory and peripheral ports) and launches the peripheral/memory
access sequences.
Priorities are managed in two stages:
• Software: each stream priority can be configured in the DMA_SxCR register. There are
four levels:
– Very high priority
– High priority
– Medium priority
– Low priority
• Hardware: If two requests have the same software priority level, the stream with the
lower number takes priority over the stream with the higher number. For example,
Stream 2 takes priority over Stream 4.
9.3.5 DMA streams
Each of the 8 DMA controller streams provides a unidirectional transfer link between a
source and a destination.
Each stream can be configured to perform:
• Regular type transactions: memory-to-peripherals, peripherals-to-memory or memory-
to-memory transfers
• Double-buffer type transactions: double buffer transfers using two memory pointers for
the memory (while the DMA is reading/writing from/to a buffer, the application can
write/read to/from the other buffer).
Table 23. DMA2 request mapping
Peripheral
requests
Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7
Channel 0 ADC1 -
TIM8_CH1
TIM8_CH2
TIM8_CH3
- ADC1 -
TIM1_CH1
TIM1_CH2
TIM1_CH3
-
Channel 1
-
DCMI ADC2 ADC2 - - - DCMI
Channel 2 ADC3 ADC3
-
- - CRYP_OUT CRYP_IN HASH_IN
Channel 3 SPI1_RX
-
SPI1_RX SPI1_TX
-
SPI1_TX
--
Channel 4 - - USART1_RX SDIO
-
USART1_RX SDIO USART1_TX
Channel 5
-
USART6_RX USART6_RX - -
-
USART6_TX USART6_TX
Channel 6 TIM1_TRIG TIM1_CH1 TIM1_CH2 TIM1_CH1
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM1_UP TIM1_CH3
-
Channel 7
-
TIM8_UP TIM8_CH1 TIM8_CH2 TIM8_CH3 - -
TIM8_CH4
TIM8_TRIG
TIM8_COM

ST STM32F207 series Specifications

General

Brand	ST
Model	STM32F207 series
Category	Microcontrollers
Language	English