ST STM32F207 series - Figure 76. Counter Timing Diagram, Internal Clock Divided by 4; Figure 77. Counter Timing Diagram, Internal Clock Divided by N

RM0033 Rev 9 313/1381
RM0033 Advanced-control timers (TIM1 and TIM8)
375
Figure 76. Counter timing diagram, internal clock divided by 4
Figure 77. Counter timing diagram, internal clock divided by N
MS40510V1
0036
00350001 0000
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag (UIF)
CNT_EN
001F20
MS31187V1
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
36