ST STM32F207 series - Debug Mode; Timer Synchronization (TIM9;12)

General-purpose timers (TIM9 to TIM14) RM0033
458/1381 RM0033 Rev 9
15.3.12 Timer synchronization (TIM9/12)
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 14.3.15: Timer synchronization for details.
Note: The clock of the slave timer must be enabled prior to receive events from the master timer,
and must not be changed on-the-fly while triggers are received from the master timer.
15.3.13 Debug mode
When the microcontroller enters debug mode (Cortex
®
-M3 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 32.16.2: Debug support for timers,
watchdog, bxCAN and I
2
C.