ST STM32F207 series - Figure 129. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0 X36; Figure 130. Counter Timing Diagram, Internal Clock Divided by N

RM0033 Rev 9 387/1381
RM0033 General-purpose timers (TIM2 to TIM5)
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Figure 129. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 130. Counter timing diagram, internal clock divided by N
MS37344V1
0034 0035
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow (cnt_ovf)
Update interrupt flag (UIF)
CNT_EN
0036 0035
MS37345V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Update interrupt flag (UIF)
Counter underflow
001F20 01