ST STM32F207 series - Figure 222. I2 C Interrupt Mapping Diagram

Inter-integrated circuit (I2C) interface RM0033
616/1381 RM0033 Rev 9
Note: SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically OR-ed on the same interrupt
channel.
BERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically OR-ed on the
same interrupt channel.
Figure 222. I
2
C interrupt mapping diagram
Bus error BERR
ITERREN
Arbitration loss (Master) ARLO
Acknowledge failure AF
Overrun/Underrun OVR
PEC error PECERR
Timeout/Tlow error TIMEOUT
SMBus Alert SMBALERT
Table 82. I
2
C Interrupt requests (continued)
Interrupt event Event flag Enable control bit
ADDR
SB
ADD10
RxNE
TxE
BTF
it_event
ARLO
BERR
AF
OVR
PECERR
TIMEOUT
SMBALERT
ITERREN
it_error
ITEVFEN
ITBUFEN
STOPF
MS42082V1