Serial peripheral interface (SPI) RM0033
720/1381 RM0033 Rev 9
For more details about the read operations depending on the I
2
S standard mode selected,
refer to Section 25.4.2: Supported audio protocols.
If data are received while the previously received data have not been read yet, an overrun is
generated and the OVR flag is set. If the ERRIE bit is set in the SPI_CR2 register, an
interrupt is generated to indicate the error.
To switch off the I
2
S, specific actions are required to ensure that the I
2
S completes the
transfer cycle properly without initiating a new data transfer. The sequence depends on the
configuration of the data and channel lengths, and on the audio protocol mode selected. In
the case of:
• 16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1)
using the LSB justified mode (I2SSTD = 10)
a) Wait for the second to last RXNE = 1 (n – 1)
b) Then wait 17 I
2
S clock cycles (using a software loop)
c) Disable the I
2
S (I2SE = 0)
• 16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) in
MSB justified, I
2
S or PCM modes (I2SSTD = 00, I2SSTD = 01 or I2SSTD = 11,
respectively)
a) Wait for the last RXNE
b) Then wait 1 I
2
S clock cycle (using a software loop)
c) Disable the I
2
S (I2SE = 0)
• For all other combinations of DATLEN and CHLEN, whatever the audio mode selected
through the I2SSTD bits, carry out the following sequence to switch off the I
2
S:
a) Wait for the second to last RXNE = 1 (n – 1)
b) Then wait one I
2
S clock cycle (using a software loop)
c) Disable the I
2
S (I2SE = 0)
Note: The BSY flag is kept low during transfers.
25.4.5 I
2
S slave mode
In slave mode, the I
2
S can be configured in transmission or reception mode.The operating
mode is following mainly the same rules as described for the I
2
S master configuration. In
slave mode, there is no clock to be generated by the I
2
S interface. The clock and WS
signals are input from the external master connected to the I
2
S interface. There is then no
need, for the user, to configure the clock.
The configuration steps to follow are listed below:
1. Set the I2SMOD bit in the SPI_I2SCFGR register to reach the I
2
S functionalities and
choose the I
2
S standard through the I2SSTD[1:0] bits, the data length through the
DATLEN[1:0] bits and the number of bits per channel for the frame configuring the
CHLEN bit. Select also the mode (transmission or reception) for the slave through the
I2SCFG[1:0] bits in SPI_I2SCFGR register.
2. If needed, select all the potential interrupt sources and the DMA capabilities by writing
the SPI_CR2 register.
3. The I2SE bit in SPI_I2SCFGR register must be set.
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