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General-purpose timers (TIM2 to TIM5) RM0033

386/1381 RM0033 Rev 9

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC

• The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that if the update source is a counter overflow, the auto-

reload is updated before the counter is reloaded, so that the next period is the expected

one (the counter is loaded with the new value).

The following figures show some examples of the counter behavior for different clock

frequencies.

Figure 127. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

1. Here, center-aligned mode 1 is used, for more details refer to Section 14.4.1: TIMx control register 1 (TIMx_CR1).

Figure 128. Counter timing diagram, internal clock divided by 2

MS37342V1

CK_INT

Timerclock = CK_CNT

Counter register

Update event (UEV)

Counter overflow

Update interrupt flag (UIF)

CNT_EN

Counter underflow

00020304 05 0601 02 03 0401 05 0304

MS37343V1