RM0033 Rev 9 1283/1381
RM0033 Flexible static memory controller (FSMC)
1318
3-2 MTYP[0:1] As needed
1 MUXEN 0x0
0 MBKEN 0x1
Table 191. FSMC_BTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x3
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for
read accesses.
7-4 ADDHLD
Duration of the middle phase of the read access (ADDHLD HCLK
cycles)
3-0 ADDSET[3:0]
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 1.
Table 192. FSMC_BWTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x3
27-24 DATLAT 0x0
23-20 CLKDIV 0x0
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST Duration of the second access phase
7-4 ADDHLD
Duration of the middle phase of the write access (ADDHLD HCLK
cycles)
3-0 ADDSET[3:0] Duration of the first access phase . Minimum value for ADDSET is 1.
Table 190. FSMC_BCRx bit fields (continued)
Bit No. Bit name Value to set
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