DMA controller (DMA) RM0033
180/1381 RM0033 Rev 9
After an event, the peripheral sends a request signal to the DMA controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the
DMA controller. The peripheral releases its request as soon as it gets the Acknowledge
signal from the DMA controller. Once the request has been deasserted by the peripheral,
the DMA controller releases the Acknowledge signal. If there are more requests, the
peripheral can initiate the next transaction.
9.3.3 Channel selection
Each stream is associated with a DMA request that can be selected out of 8 possible
channel requests. The selection is controlled by the CHSEL[2:0] bits in the DMA_SxCR
register.
Figure 23. Channel selection
The 8 requests from the peripherals (TIM, ADC, SPI, I2C, etc.) are independently connected
to each channel and their connection depends on the product implementation.
See the following table(s) for examples of DMA request mappings.
REQ_STREAMx
REQ_STRx_CH7
CHSEL[2:0]
3 1 2 7 25 0
DMA_SxCR
ai15947b
REQ_STRx_CH6
REQ_STRx_CH5
REQ_STRx_CH4
REQ_STRx_CH3
REQ_STRx_CH2
REQ_STRx_CH1
REQ_STRx_CH0
Table 22. DMA1 request mapping
Peripheral
requests
Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7
Channel 0 SPI3_RX
-
SPI3_RX SPI2_RX SPI2_TX SPI3_TX
-
SPI3_TX
Channel 1 I2C1_RX
-
TIM7_UP
-
TIM7_UP I2C1_RX I2C1_TX I2C1_TX
Channel 2 TIM4_CH1
-
I2S3_ext_RX TIM4_CH2 I2S2_ext_TX I2S3_ext_TX TIM4_UP TIM4_CH3
Channel 3 I2S3_ext_RX
TIM2_UP
TIM2_CH3
I2C3_RX I2S2_ext_RX I2C3_TX TIM2_CH1
TIM2_CH2
TIM2_CH4
TIM2_UP
TIM2_CH4
Channel 4 UART5_RX USART3_RX UART4_RX USART3_TX UART4_TX USART2_RX USART2_TX UART5_TX
Channel 5
--
TIM3_CH4
TIM3_UP
-
TIM3_CH1
TIM3_TRIG
TIM3_CH2
-
TIM3_CH3
Channel 6
TIM5_CH3
TIM5_UP
TIM5_CH4
TIM5_TRIG
TIM5_CH1
TIM5_CH4
TIM5_TRIG
TIM5_CH2
-
TIM5_UP
-
Channel 7
-
TIM6_UP I2C2_RX I2C2_RX USART3_TX DAC1 DAC2 I2C2_TX
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