DMA controller (DMA) RM0033
190/1381 RM0033 Rev 9
9.3.12 FIFO
FIFO structure
The FIFO is used to temporarily store data coming from the source before transmitting them
to the destination.
Each stream has an independent 4-word FIFO and the threshold level is software-
configurable between 1/4, 1/2, 3/4 or full.
To enable the use of the FIFO threshold level, the direct mode must be disabled by setting
the DMDIS bit in the DMA_SxFCR register.
The structure of the FIFO differs depending on the source and destination data widths, and
is described in Figure 27: FIFO structure.
Figure 27. FIFO structure
Source: byte
4 words
byte lane 0
byte lane 1
byte lane 2
byte lane 3
1/4 1/2 3/4 FullEmpty
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B 11
B12
B13
B14
B15
Destination: word
Source: byte
Destination: half-word
4 words
byte lane 0
byte lane 1
byte lane 2
byte lane 3
1/4 1/2 3/4 FullEmpty
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B 11
B12
B13
B14
B15
W0W1W2W3
H0
H1
H2
H3
H4
H5
H6
H7
Source: half-word
Destination: word
4 words
byte lane 0
byte lane 1
byte lane 2
byte lane 3
1/4 1/2 3/4 FullEmpty
H0
W0W1W2W3
H1
H2
H3
H4
H5
H6
H7
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
H7 H6 H5 H4 H3 H2 H1 H0
H7, H6, H5, H4, H3, H2, H1, H0
W3, W2, W1, W0
W3, W2, W1, W0
Source: half-word
4-words
byte lane 0
byte lane 1
byte lane 2
byte lane 3
1/4 1/2 3/4 FullEmpty
Destination: byte
H7 H6 H5 H4 H3 H2 H1 H0
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B 11
B12
B13
B14
B15
H0
H1
H2
H3
H4
H5
H6
H7
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
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