Reset and clock control (RCC) RM0033
84/1381 RM0033 Rev 9
5 Reset and clock control (RCC)
5.1 Reset
There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.
5.1.1 System reset
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 8).
"A system reset sets all registers to their reset values unless specified otherwise in the
register description
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see Software reset)
5. Low-power management reset (see Low-power management reset)
Software reset
The reset source can be identified by checking the reset flags in the RCC clock control &
status register (RCC_CSR).
The SYSRESETREQ bit in Cortex
®
-M3 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the Cortex™-M3 technical
reference manual for more details.
To Next Page
Loading...
Need help?
General
