ST STM32F207 series User Manual

Reset and clock control (RCC) RM0033
104/1381 RM0033 Rev 9
5.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
OTGHS
RST
Reserved
ETHMAC
RST
Reserved
DMA2
RST
DMA1
RST
Reserved
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CRCRS
T
Reserved
GPIOI
RST
GPIOH
RST
GPIOGG
RST
GPIOF
RST
GPIOE
RST
GPIOD
RST
GPIOC
RST
GPIOB
RST
GPIOA
RST
rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, always read as 0.
Bit 29 OTGHSRST: USB OTG HS module reset
Set and cleared by software.
0: does not reset the USB OTG HS module
1: resets the USB OTG HS module
Bits 28:26 Reserved, always read as 0.
Bit 25 ETHMACRST: Ethernet MAC reset
Set and cleared by software.
0: does not reset Ethernet MAC
1: resets Ethernet MAC
Bits 24:23 Reserved, always read as 0
Bit 22 DMA2RST: DMA2 reset
Set and cleared by software.
0: does not reset DMA2
1: resets DMA2
Bit 21 DMA1RST: DMA2 reset
Set and cleared by software.
0: does not reset DMA2
1: resets DMA2
Bits 20:13 Reserved, always read as 0.
Bit 12 CRCRST: CRC reset
Set and cleared by software.
0: does not reset CRC
1: resets CRC
Bits 11:9 Reserved, always read as 0

ST STM32F207 series Specifications

General

Brand	ST
Model	STM32F207 series
Category	Microcontrollers
Language	English