Debug support (DBG) RM0033
1332/1381 RM0033 Rev 9
32.8.6 SW-AP registers
Access to these registers are initiated when APnDP=1
There are many AP registers (see AHB-AP) addressed as the combination of:
• The shifted value A[3:2]
• The current value of the DP SELECT register
32.9 AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP
Features:
• System access is independent of the processor status.
• Either SW-DP or JTAG-DP accesses AHB-AP.
• The AHB-AP is an AHB master into the Bus Matrix. Consequently, it can access all the
data buses (Dcode Bus, System Bus, internal and external PPB bus) but the ICode
bus.
• Bitband transactions are supported.
• AHB-AP transactions bypass the FPB.
The address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes)
and consists of:
c) Bits [7:4] = the bits [7:4] APBANKSEL of the DP SELECT register
d) Bits [3:2] = the 2 address bits of A[3:2] of the 35-bit packet request for SW-DP.
The AHB-AP of the Cortex
®
-M3 includes 9 x 32-bits registers:
Refer to the Cortex
®
-M3 r2p0 TRM for further details.
Table 215. Cortex
®
-M3 AHB-AP registers
Address
offset
Register name Notes
0x00
AHB-AP Control and Status
Word
Configures and controls transfers through the AHB
interface (size, hprot, status on current transfer, address
increment type
0x04 AHB-AP Transfer Address -
0x0C AHB-AP Data Read/Write -
0x10 AHB-AP Banked Data 0
Directly maps the 4 aligned data words without rewriting
the Transfer Address register.
0x14 AHB-AP Banked Data 1
0x18 AHB-AP Banked Data 2
0x1C AHB-AP Banked Data 3
0xF8 AHB-AP Debug ROM Address Base Address of the debug interface
0xFC AHB-AP ID register -
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