General-purpose timers (TIM2 to TIM5) RM0033
392/1381 RM0033 Rev 9
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 137. Control circuit in external clock mode 2
14.3.4 Capture/compare channels
Each Capture/Compare channel (see Figure 138) is built around a capture/compare register
(including a shadow register), an input stage for capture (with digital filter, multiplexing and
prescaler) and an output stage (with comparator and output control).
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Figure 138. Capture/compare channel (example: channel 1 input stage)
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
MS37362V1
34 35 36
CNT_EN
ETR
ETRP
ETRF
Counter clock = CK_INT =CK_PSC
Counter register
CK_INT
TI1
TIMx_CCER
CC1P/CC1NP
divider
/1, /2, /4, /8
ICPS[1:0]
TI1F_ED
filter
ICF[3:0]
downcounter
TIMx_CCMR1
Edge
Detector
TI1F_Rising
TI1F_Falling
to the slave mode controller
TI1FP1
11
01
TIMx_CCMR1
CC1S[1:0]
IC1
TI2FP1
TRC
(from channel 2)
(from slave mode
controller)
10
f
DTS
TIMx_CCER
CC1E
IC1PS
TI1F
TI2F_rising
TI2F_falling
(from channel 2)
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