RM0033 Rev 9 573/1381
RM0033 Real-time clock (RTC)
597
f
ck_spre
is given by the following formula:
The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit
wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload
timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous
prescaler (see
Section 22.3.4: Periodic auto-wakeup for details).
22.3.2 Real-time clock and calendar
The RTC calendar time and date registers are accessed through shadow registers which
are synchronized with PCLK1 (APB1 clock).
• RTC_TR for the time
• RTC_DR for the date
Every two RTCCLK periods, the current calendar value is copied into the shadow registers,
and the RSF bit of RTC_ISR register is set (see
Section 22.6.4). The copy is not performed
in Stop and Standby mode. When exiting these modes, the shadow registers are updated
after up to 2 RTCCLK periods.
When the application reads the calendar registers, it accesses the content of the shadow
registers.
When reading the RTC_TR or RTC_DR registers, the frequency of the APB clock (f
APB
)
must be at least 7 times the frequency of the RTC clock (f
RTCCLK
).
The shadow registers are reset by system reset.
22.3.3 Programmable alarms
The RTC unit provides two programmable alarms, Alarm A and Alarm B.
The programmable alarm functions are enabled through the ALRAIE and ALRBIE bits in the
RTC_CR register. The ALRAF and ALRBF flags are set to 1 if the calendar seconds,
minutes, hours, date or day match the values programmed in the alarm registers
RTC_ALRMAR and RTC_ALRMBR, respectively. Each calendar field can be independently
selected through the MSKx bits of the RTC_ALRMAR and RTC_ALRMBR registers. The
alarm interrupts are enabled through the ALRAIE and ALRBIE bits in the RTC_CR register.
Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the
AFO_ALARM output. AFO_ALARM polarity can be configured through bit POL in the
RTC_CR register.
Caution: If the seconds field is selected (MSK0 bit reset in RTC_ALRMAR or RTC_ALRMBR), the
synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to
ensure correct behavior.
22.3.4 Periodic auto-wakeup
The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter.
The wakeup timer range can be extended to 17 bits.
The wakeup function is enabled through the WUTE bit in the RTC_CR register.
f
CK_SPRE
f
RTCCLK
PREDIV_S 1+()PREDIV_A 1+()×
----------------------------------------------------------------------------------------------=
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