Power control (PWR) RM0033
66/1381 RM0033 Rev 9
When the backup domain is supplied by V
DD
(analog switch connected to V
DD
), the
following functions are available:
• PC14 and PC15 can be used as either GPIO or LSE pins
• PC13 can be used as a GPIO or as the RTC_AF1 pin (refer to Table 16: RTC_AF1 pin
for more details about this pin configuration)
• PI8 can be used as a GPIO or as the RTC_AF2 pin (refer to Table 17: RTC_AF2 pin for
more details about this pin configuration)
Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PC13 to PC15 and PI8 are restricted: only one I/O at a time can be used as an
output, the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os
must not be used as a current source (e.g. to drive an LED).
When the backup domain is supplied by V
BAT
(analog switch connected to V
BAT
because
V
DD
is not present), the following functions are available:
• PC14 and PC15 can be used as LSE pins only
• PC13 can be used as the RTC_AF1 pin (refer to Table 16: RTC_AF1 pin) for more
details about this pin configuration)
• PI8 can be used as the RTC_AF2 pin (refer to Table 17: RTC_AF2 pin for more details
about this pin configuration)
Backup domain access
After reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is
protected against possible unwanted write accesses. To enable access to the backup
domain, proceed as follows:
• Access to the RTC and RTC backup registers
1. Enable the power interface clock by setting the PWREN bits in the RCC APB1
peripheral clock enable register (RCC_APB1ENR)
2. Set the DBP bit in the PWR power control register (PWR_CR) to enable access to the
backup domain
3. Select the RTC clock source: see Section 5.2.8: RTC/AWU clock
4. Enable the RTC clock by programming the RTCEN [15] bit in the RCC Backup domain
control register (RCC_BDCR)
• Access to the backup SRAM
1. Enable the power interface clock by setting the PWREN bits in the RCC APB1
peripheral clock enable register (RCC_APB1ENR)
2. Set the DBP bit in the PWR power control register (PWR_CR) to enable access to the
backup domain
3. Enable the backup SRAM clock by setting BKPSRAMEN bit in the RCC AHB1
peripheral clock register (RCC_AHB1ENR)
RTC and RTC backup registers
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes)
which are reset when a tamper detection event occurs. For more details refer to Section 22:
Real-time clock (RTC).
To Next Page
Loading...
Need help?
General
