ST STM32F207 series - TIM1 and TIM8 Auto-Reload Register (Timx_Arr); TIM1 and TIM8 Counter (Timx_Cnt); TIM1 and TIM8 Prescaler (Timx_Psc)

RM0033 Rev 9 367/1381
RM0033 Advanced-control timers (TIM1 and TIM8)
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13.4.10 TIM1 and TIM8 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
13.4.11 TIM1 and TIM8 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
13.4.12 TIM1 and TIM8 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF
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CNT[15:0]
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Bits 15:0 CNT[15:0]: Counter value
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PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
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ARR[15:0]
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Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 13.3.1: Time-base unit for more details about ARR update and behavior.
The counter is blocked while the auto-reload value is null.