ST STM32F207 series User Manual

Reset and clock control (RCC) RM0033
118/1381 RM0033 Rev 9
5.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)
Address offset: 0x44
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TIM11
EN
TIM10
EN
TIM9
EN
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reser-
ved
SYSCF
G EN
Reser-
ved
SPI1
EN
SDIO
EN
ADC3
EN
ADC2
EN
ADC1
EN
Reserved
USART6
EN
USART1
EN
Reserved
TIM8
EN
TIM1
EN
rw rw rw rw rw rw rw rw rw rw
Bits 31:19 Reserved, always read as 0.
Bit 18 TIM11EN: TIM11 clock enable
Set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Bit 17 TIM10EN: TIM10 clock enable
Set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
Bit 16 TIM9EN: TIM9 clock enable
Set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
Bit 15 Reserved, always read as 0.
Bit 14 SYSCFGEN: System configuration controller clock enable
Set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
Bit 13 Reserved, always read as 0.
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 SDIOEN: SDIO clock enable
Set and cleared by software.
0: SDIO module clock disabled
1: SDIO module clock enabled
Bit 10 ADC3EN: ADC3 clock enable
Set and cleared by software.
0: ADC3 clock disabled
1: ADC3 clock disabled

ST STM32F207 series Specifications

General

Brand	ST
Model	STM32F207 series
Category	Microcontrollers
Language	English