Interrupts and events RM0033
164/1381 RM0033 Rev 9
8 Interrupts and events
This Section applies to the whole STM32F20x and STM32F21x family, unless otherwise
specified.
8.1 Nested vectored interrupt controller (NVIC)
8.1.1 NVIC features
The nested vector interrupt controller NVIC includes the following features:
• 81 maskable interrupt channels (not including the 16 interrupt lines of Cortex
®
-M3)
• 16 programmable priority levels (4 bits of interrupt priority are used)
• low-latency exception and interrupt handling
• power management control
• implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to PM0056 programming manual.
8.1.2 SysTick calibration value register
The SysTick calibration value is fixed to 15000, which gives a reference time base of 1 ms
with the SysTick clock set to 15 MHz (max HCLK/8).
8.1.3 Interrupt and exception vectors
Table 2 0 is the vector table for the STM32F20x and STM32F21x devices.
Table 20. Vector table
Position
Priority
Type of
priority
Acronym Description Address
- - - Reserved 0x0000_0000
-3 fixed Reset Reset 0x0000_0004
-2 fixed NMI
Non maskable interrupt. The RCC
Clock Security System (CSS) is
linked to the NMI vector.
0x0000_0008
-1 fixed HardFault All class of fault 0x0000_000C
0 settable MemManage Memory management 0x0000_0010
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