Inter-integrated circuit (I2C) interface RM0033
598/1381 RM0033 Rev 9
23 Inter-integrated circuit (I2C) interface
This section applies to the whole STM32F20x and STM32F21x family, unless otherwise
specified.
23.1 I
2
C introduction
I
2
C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller
and the serial I
2
C bus. It provides multimaster capability, and controls all I
2
C bus-specific
sequencing, protocol, arbitration and timing. It supports the standard mode (Sm, up to
100 kHz) and Fm mode (Fm, up to 400 kHz).
It may be used for a variety of purposes, including CRC generation and verification, SMBus
(system management bus) and PMBus (power management bus).
Depending on specific device implementation DMA capability can be available for reduced
CPU overload.
23.2 I
2
C main features
• Parallel-bus/I
2
C protocol converter
• Multimaster capability: the same interface can act as Master or Slave
• I
2
C Master features:
– Clock generation
– Start and Stop generation
• I
2
C Slave features:
– Programmable I
2
C Address detection
– Dual Addressing Capability to acknowledge 2 slave addresses
– Stop bit detection
• Generation and detection of 7-bit/10-bit addressing and General Call
• Supports different communication speeds:
– Standard Speed (up to 100 kHz)
– Fast Speed (up to 400 kHz)
• Analog noise filter
• Status flags:
– Transmitter/Receiver mode flag
– End-of-Byte transmission flag
–I
2
C busy flag
• Error flags:
– Arbitration lost condition for master mode
– Acknowledgment failure after address/ data transmission
– Detection of misplaced start or stop condition
– Overrun/Underrun if clock stretching is disabled
• 2 Interrupt vectors:
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