ST STM32F207 series User Manual

RM0033 Rev 9 987/1381
RM0033 USB on-the-go full-speed (OTG_FS)
1097
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device
modes.
... ... ...
Device IN Endpoint x
(1)
/Host OUT Channel x
(1)
: DFIFO Write Access
Device OUT Endpoint x
(1)
/Host IN Channel x
(1)
: DFIFO Read Access
0xX000–0xXFFC
w
r
1. Where x is 3 in device mode and 7 in host mode.
Table 155. Power and clock gating control and status registers
Register name Acronym Offset address: 0xE00–0xFFF
Power and clock gating control register OTG_FS_PCGCCTL 0xE00-0xE04
Reserved - 0xE05–0xFFF
Table 154. Data FIFO (DFIFO) access register map (continued)
FIFO access register section Address range Access

ST STM32F207 series Specifications

General

Brand	ST
Model	STM32F207 series
Category	Microcontrollers
Language	English