ST STM32F207 series - Figure 186. Counter Timing Diagram, Internal Clock Divided by 2; Figure 187. Counter Timing Diagram, Internal Clock Divided by 4; Figure 188. Counter Timing Diagram, Internal Clock Divided by N

Basic timers (TIM6 and TIM7) RM0033
488/1381 RM0033 Rev 9
Figure 186. Counter timing diagram, internal clock divided by 2
Figure 187. Counter timing diagram, internal clock divided by 4
Figure 188. Counter timing diagram, internal clock divided by N
MS35835V1
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
0034 0035 0036 0000 0001 0002 0003
0000 00010035 0036
MSv37301V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
CNT_EN
MSv37302V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
001F 20