Revision history RM0033
1352/1381 RM0033 Rev 9
34 Revision history
Table 224. Document revision history
Date Version Changes
06-Jul-2010 1 Initial release.
09-Dec-2010 2
Removed V
DDSA
from the whole document.
Updated Figure 1: System architecture for FSMC Static MemCtl.
Updated Table 3: Number of wait states according to Cortex-M3
clock frequency. Updated embedded Flash memory organization in
Section 2.3.3; updated LATENCY bits in Section : Flash access
control register (FLASH_ACR) to support up to 7 wait states; added
Section 2.3.5: Adaptive real-time memory accelerator (ART
Accelerator™).
Renamed FSMC NOR/SRAM 1/2 Bank1 into FSMC Bank1
NOR/PSRAM 1/2. Updated last two address ranges and added
Note 1 in Table 5: Memory mapping vs. Boot mode/physical remap.
Power control (PWR)
Updated Figure 3: Power supply overview.
Updated V
REF
range in Section 4.1.1: Independent A/D converter
supply and reference voltage; BOR default status updated in
Section 4.2.2: Brownout reset (BOR).
Reset and clock controller
Changed HSE oscillator frequency to 4-26 MHz and replaced
SPI2S_CKIN by I2S2_CKIN/I2S3_CKIN in Figure 9: Clock tree.
Added note related to RTC_TR register read in Section 5.2.8:
RTC/AWU clock.
Extended PLL input frequency to 2 MHz, and updated caution note
related to PLLM[5:0] bit in Section 5.3.2: RCC PLL configuration
register (RCC_PLLCFGR).
System configuration controller
Added Section 7.1: I/O compensation cell in Section 7: System
configuration controller (SYSCFG).
Added case of FSMC remapped at address 0x0000 0000, and
updated description of SYSCFG_MEMRMP register and
MEM_MODE bit in Section 7.2.1: SYSCFG memory remap register
(SYSCFG_MEMRMP).
Removed not related to READY bit in Section 7.2.7: Compensation
cell control register (SYSCFG_CMPCR).
ADC
Updated V
DDA
low-speed and V
REF
ranges in Table 32: ADC pins
Updated Section 10.2: ADC main features.
Updated Section 10.3.2: ADC clock.
Changed PCLK to PCLK2 for ADCPRE bit description in
Section 10.13.16: ADC common control register (ADC_CCR).
Updated JSQ bit description, and added note in Section 10.13.12:
ADC injected sequence register (ADC_JSQR).
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