ST STM32F207 series - Figure 325. Transmission Bit Order; Figure 326. Transmission with no Collision

Ethernet (ETH): media access control (MAC) with DMA controller RM0033
860/1381 RM0033 Rev 9
Figure 325. Transmission bit order
MII/RMII transmit timing diagrams
Figure 326. Transmission with no collision
D0
D1
D2
D3
LSB
MII_TXD[3:0]
MSB
D0 D1
LSB MSB
RMII_TXD[1:0]
Bibit stream
Nibble stream
ai1563
2
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
PR EA MB LE
MII_CS
MII_COL
ai1563
1
Low