RM0033 Rev 9 489/1381
RM0033 Basic timers (TIM6 and TIM7)
495
Figure 189. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
Figure 190. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
16.3.3 Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 191 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
FF 36
MSv37303V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
00 02 03 04 05 06 0732 33 34 35 3631 01
CNT_EN
Auto-reload register
Write a new value in TIMx_ARR
MSv37304V1
F5 36
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
00 02 03 04 05 06 07F1 F2 F3 F4 F5F0 01
CNT_EN
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload shadow register
F5 36
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