ST STM32F207 series - Figure 118. Counter Timing Diagram, Internal Clock Divided by 4; Figure 119. Counter Timing Diagram, Internal Clock Divided by N

RM0033 Rev 9 381/1381
RM0033 General-purpose timers (TIM2 to TIM5)
436
Figure 118. Counter timing diagram, internal clock divided by 4
Figure 119. Counter timing diagram, internal clock divided by N
0000 00010035 0036
MSv37301V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
CNT_EN
MSv37302V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
001F 20