ST STM32F207 series - Figure 276. Operations Required to Transmit 0 X3478 Ae; Figure 277. Operations Required to Receive 0 X3478 Ae; Figure 278. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0

Serial peripheral interface (SPI) RM0033
714/1381 RM0033 Rev 9
Figure 276. Operations required to transmit 0x3478AE
• In reception mode:
If data 0x3478AE are received, two successive read operations from SPI_DR are
required on each RXNE event.
Figure 277. Operations required to receive 0x3478AE
Figure 278. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0
When 16-bit data frame extended to 32-bit channel frame is selected during the I
2
S
configuration phase, Only one access to SPI_DR is required. The 16 remaining bits are
forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it corresponds
to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in Figure 279 is required.
0xXX34
0x78AE
First write to Data register
conditioned by TXE=1
Second write to Data register
conditioned by TXE=1
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.
MS19596V1
0xXX34
0x78AE
First read from Data register
conditioned by RXNE=1
Second read from Data register
conditioned by RXNE=1
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.
MS19597V1
MS30105V1
CK
WS
SD
Transmission
Reception
16-bit data
0 forced
MSB
LSB
Channel left 32-bit
Channel right
16-bit remaining