ST STM32F207 series User Manual

Ethernet (ETH): media access control (MAC) with DMA controller RM0033
896/1381 RM0033 Rev 9
The DMA does not acknowledge accepting the status until it has completed the time stamp
write-back and is ready to perform status write-back to the descriptor. If software has
enabled time stamping through CSR, when a valid time stamp value is not available for the
frame (for example, because the receive FIFO was full before the time stamp could be
written to it), the DMA writes all ones to RDES2 and RDES3. Otherwise (that is, if time
stamping is not enabled), RDES2 and RDES3 remain unchanged.
Figure 344. Receive DMA operation
(Re-)Fetch next
descriptor
(AHB)
error?
No
Own bit set?
Yes
Yes
Stop RxDMAStart RxDMA Start
(AHB)
error?
No
RxDMA suspended
Yes
Frame data
available?
Wait for frame dataWrite data to buffer(s)
Yes
Yes
Fetch next descriptor
Yes
No
Frame transfer
complete?
No
Set descriptor error
Yes
Time stamp
present?
No
Close RDES0 as last
descriptor
Write time stamp to
RDES2 & RDES3
No
(AHB)
error?
Yes
Close RDES0 as
intermediate descriptor
Frame transfer
complete?
No
Flush disabled ?
No
Flush the
remaining frame
Yes
Yes
No
No
No
Yes
Yes
Poll demand/
new frame available
No
Yes
(AHB)
error?
(AHB)
error?
No
Own bit set
for next desc?
Flush
disabled?
ai1564
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ST STM32F207 series Specifications

General

Brand	ST
Model	STM32F207 series
Category	Microcontrollers
Language	English