RM0033 Rev 9 733/1381
RM0033 Serial peripheral interface (SPI)
734
25.5.9 SPI_I
2
S prescaler register (SPI_I2SPR)
Address offset: 0x20
Reset value: 0000 0010 (0x0002)
1514131211109 876543210
Reserved
MCKOE ODD I2SDIV
rw rw rw
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 MCKOE: Master clock output enable
0: Master clock output is disabled
1: Master clock output is enabled
Note: This bit should be configured when the I
2
S is disabled. It is used only when the I
2
S is in master
mode.
This bit is not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: real divider value is = I2SDIV *2
1: real divider value is = (I2SDIV * 2)+1
Refer to Section 25.4.3: Clock generator. Not used in SPI mode.
Note: This bit should be configured when the I
2
S is disabled. It is used only when the I
2
S is in master
mode.
Bits 7:0 I2SDIV: I2S Linear prescaler
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to Section 25.4.3: Clock generator. Not used in SPI mode.
Note: These bits should be configured when the I
2
S is disabled. It is used only when the I
2
S is in
master mode.
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