ST STM32F207 series - Figure 250. Data Clock Timing Diagram

Serial peripheral interface (SPI) RM0033
688/1381 RM0033 Rev 9
Figure 250. Data clock timing diagram
1. These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.
Data frame format
Data can be shifted out either MSB-first or LSB-first depending on the value of the
LSBFIRST bit in the SPI_CR1 register.
Each data frame is 8 or 16 bits long depending on the size of the data programmed using
the DFF bit in the SPI_CR1 register. The selected data frame format is applicable for
transmission and/or reception.
CPOL = 1
CPOL = 0
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
NSS
(to slave)
Capture strobe
CPHA =1
CPOL = 1
CPOL = 0
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
NSS
(to slave)
Capture strobe
CPHA =0
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