Cryptographic processor (CRYP) RM0033
510/1381 RM0033 Rev 9
19.3 CRYP functional description
The cryptographic processor implements a Triple-DES (TDES, that also supports DES) core
and an AES cryptographic core. Section 19.3.1 and Section 19.3.2 provide details on these
cores.
Since the TDES and the AES algorithms use block ciphers, incomplete input data blocks
have to be padded prior to encryption (extra bits should be appended to the trailing end of
the data string). After decryption, the padding has to be discarded. The hardware does not
manage the padding operation, the software has to handle it.
Figure 195 shows the block diagram of the cryptographic processor.
Figure 195. Block diagram
19.3.1 DES/TDES cryptographic core
The DES/Triple-DES cryptographic core consists of three components:
• The DES algorithm (DEA)
• Multiple keys (1 for the DES algorithm, 1 to 3 for the TDES algorithm)
• The initialization vector (used in the CBC mode)
The basic processing involved in the TDES is as follows: an input block is read in the DEA
and encrypted using the first key, K1 (K0 is not used in TDES mode). The output is then
decrypted using the second key, K2, and encrypted using the third key, K3. The key
depends on the algorithm which is used:
• DES mode: Key = [K1]
• TDES mode: Key = [K3 K2 K1]
where Kx=[KxR KxL], R = right, L = left
32-bit AHB2 bus
Processor core
DES/TDES/AES
CRYP_DIN
swappi ng
sw appin g
8 × 32-bit
IN FIFO
8 × 32-bit
OUT FIFO
CRYP_CR
CRYP_K0. ..K3
CRYP_IV0...IV1
IV0...IV127
k255...k0
CRYP_IMSCR
CRYP_RIS
CRYP_MISR
CRYP_DMACR
CRYP_SR
Status
DMA control register
Interrupt registers
Control register
Initialization vectors
Key
ai16068b
CRYP_DOUT
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