ST STM32F207 series User Manual

Digital-to-analog converter (DAC) RM0033
276/1381 RM0033 Rev 9
11.5.14 DAC status register (DAC_SR)
Address offset: 0x34
Reset value: 0x0000 0000
11.5.15 DAC register map
Table 43 summarizes the DAC registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DMAUDR2
Reserved
rc_w1
1514 13 1211109876543210
Reserved
DMAUDR1
Reserved
rc_w1
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DMAUDR2: DAC channel2 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel2
1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is
driving DAC channel2 conversion at a frequency higher than the DMA service capability rate)
Bits 28:14 Reserved, must be kept at reset value.
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bits 12:0 Reserved, must be kept at reset value.
Table 43. DAC register map
Offset Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
11
10
9 8 7 6 5 4 3 2 1 0
0x00 DAC_CR
Reserved
DMAUDRIE2
DMAEN2
MAMP2[3:0]
WAVE
2[2:0]
TSEL2[2:0]
TEN2
BOFF2
EN2
Reserved
DMAUDRIE1
DMAEN1
MAMP1[3:0]
WAVE
1[2:0]
TSEL1[2
:0]
TEN1
BOFF1
EN1
0x04
DAC_
SWTRIGR
Reserved
SWTRIG2 SWTRIG1
0x08
DAC_
DHR12R1
Reserved DACC1DHR[11:0]
0x0C
DAC_
DHR12L1
Reserved DACC1DHR[11:0] Reserved
0x10
DAC_
DHR8R1
Reserved DACC1DHR[7:0]
0x14
DAC_
DHR12R2
Reserved DACC2DHR[11:0]
0x18
DAC_
DHR12L2
Reserved DACC2DHR[11:0] Reserved

ST STM32F207 series Specifications

General

Brand	ST
Model	STM32F207 series
Category	Microcontrollers
Language	English