ST STM32F207 series User Manual

RM0033 Rev 9 1287/1381
RM0033 Flexible static memory controller (FSMC)
1318
Figure 412. Asynchronous wait during a read access
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
Figure 413. Asynchronous wait during a write access
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
A[25:0]
NOE
4HCLK
Memory transaction
NWAIT
D[15:0]
NEx
data driven
by memory
ai18471b
address phase
don’t care
data setup phase
don’t care
A[25:0]
NWE
Memory transaction
NWAIT
D[15:0]
NEx
data driven by FSMC
ai15797c
3HCLK
address phase
data setup phase
1HCLK
don’t care don’t care

ST STM32F207 series Specifications

General

Brand	ST
Model	STM32F207 series
Category	Microcontrollers
Language	English