ST STM32F207 series User Manual

RM0033 Rev 9 627/1381
RM0033 Inter-integrated circuit (I2C) interface
629
23.6.8 I
2
C Clock control register (I2C_CCR)
Address offset: 0x1C
Reset value: 0x0000
Note: f
PCLK1
must be at least 2 MHz to achieve Sm mode I²C frequencies. It must be at least 4
MHz to achieve Fm mode I²C frequencies. It must be a multiple of 10MHz to reach the
400 kHz maximum I²C Fm mode clock.
The CCR register must be configured only when the I2C is disabled (PE = 0).
151413121110987 654321 0
F/S DUTY
Reserved
CCR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 F/S: I2C master mode selection
0: Sm mode I2C
1: Fm mode I2C
Bit 14 DUTY: Fm mode duty cycle
0: Fm mode t
low
/t
high
= 2
1: Fm mode t
low
/t
high
= 16/9 (see CCR)
Bits 13:12 Reserved, must be kept at reset value
Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode)
Controls the SCL clock in master mode.
Sm mode or SMBus:
T
high
= CCR * T
PCLK1
T
low
= CCR * T
PCLK1
Fm mode:
If DUTY = 0:
T
high
= CCR * T
PCLK1
T
low
= 2 * CCR * T
PCLK1
If DUTY = 1:
T
high
= 9 * CCR * T
PCLK1
T
low
= 16 * CCR * T
PCLK1
For instance: in Sm mode, to generate a 100 kHz SCL frequency:
If FREQ = 08, T
PCLK1
= 125 ns so CCR must be programmed with 0x28
(0x28 <=> 40d x 125 ns = 5000 ns.)
Note: The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum
allowed value is 0x01
t
high
= t
r(SCL)
+ t
w(SCLH)
. See device datasheet for the definitions of parameters.
t
low
= t
f(SCL)
+ t
w(SCLL)
. See device datasheet for the definitions of parameters.
I2C communication speed, fSCL ~ 1/(thigh + tlow). The real frequency may differ due to
the analog noise filter input delay.
The CCR register must be configured only when the I
2
C is disabled (PE = 0).

ST STM32F207 series Specifications

General

Brand	ST
Model	STM32F207 series
Category	Microcontrollers
Language	English