Power control (PWR) RM0033
72/1381 RM0033 Rev 9
4.3.1 Slowing down system clocks
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 5.3.3: RCC clock configuration register (RCC_CFGR).
4.3.2 Peripheral clock gating
In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be
stopped at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB1 peripheral clock enable register
(RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR), AHB3
peripheral clock enable register (RCC_AHB3ENR) (see RCC APB1 peripheral clock enable
register (RCC_APB1ENR) and RCC APB2 peripheral clock enable register
(RCC_APB2ENR)).
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.
Table 7. Low-power mode summary
Mode name Entry Wakeup
Effect on 1.2 V
domain clocks
Effect on
V
DD
domain
clocks
Voltage regulator
Sleep
(Sleep now or
Sleep-on-exit)
WFI or Return
from ISR
Any interrupt
CPU CLK OFF
no effect on other
clocks or analog
clock sources
None ON
WFE Wakeup event
Stop
PDDS and LPDS
bits +
SLEEPDEEP bit
+ WFI, Return
from ISR or WFE
Any EXTI line (configured
in the EXTI registers,
internal and external lines)
All 1.2 V domain
clocks OFF
HSI and
HSE
oscillators
OFF
ON or in low- power
mode (depends on
PWR power control
register
(PWR_CR))
Standby
PDDS bit +
SLEEPDEEP bit
+ WFI, Return
from ISR or WFE
WKUP pin rising edge,
RTC alarm (Alarm A or
Alarm B), RTC Wakeup
event, RTC tamper event,
RTC time stamp event,
external reset in NRST
pin, IWDG reset
OFF
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